Gate Electrode RC Delay Effects in VLSI´s

A poly-silicon gate electrode can be considered as a distributed RC line. The delay induced by this RC time constant can become a limitation in designing high-speed VLSI´s. This effect, called the gate electrode RC delay effect (GERDE), is studied for short-channel MOSFET´s. A simple formula is derived to roughly estimate the GERDE, which can be used as a rule-of-thumb in VLSI design. An approximation of the GERDE by a simple lumped-circuit model is also described. The future trends of the GERDE are investigated and it is concluded that the GERDE gets more severe for shorter channel MOSFET´s, but, if the gate width is confined up to 30μm, the GERDE can be neglected for MOSFET´s with a channel length of more than 0.8 μm. For a large conductance, division of the MOSFET width is shown to be effective through experiments.