Title :
A Self-Testing Dynamic RAM Chip
Author :
You, Younggap ; Hayes, John P.
Abstract :
A novel approach to making very large dynamic RAM chips self-testing is presented. It is based on two main concepts on-chip generation of regular test sequences with very high fault coverage, and concurrent testing of storage-cell arrays to reduce overall testing time. The failure modes of a typical 64K RAM employing one-transistor cells are analyzed to identify their test requirements. A comprehensive test generation algorithm that can be implemented with minimal modification to a standard cell layout is derived. The self-checking peripheral circuits necessary to implement this testing algorithm are described, and the self-testing RAM is briefly evaluated.
Keywords :
Field effect integrated circuits; Integrated circuit technology; Integrated circuit testing; Integrated memory circuits; Random-access storage; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer errors; DRAM chips; Electrical fault detection; Failure analysis; Fault detection; Read-write memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1985.1052325
