DocumentCode
898217
Title
Custom LSI/VLSI chip design productivity
Author
Fey, Curt F.
Volume
20
Issue
2
fYear
1985
fDate
4/1/1985 12:00:00 AM
Firstpage
555
Lastpage
561
Abstract
A description is given of an eight-parameter empirical model for determining design manpower for full custom digital LSI/VLSI (not standard cell or polycell). The model estimates design manpower from six generally available design characteristics. It fits the data from five different organizations with an average absolute error of 10%. Both merchant market suppliers an in-house captives are included in the sample.
Keywords
Digital integrated circuits; Field effect integrated circuits; Integrated circuit technology; Large scale integration; VLSI; digital integrated circuits; field effect integrated circuits; integrated circuit technology; large scale integration; Chip scale packaging; Costs; Design methodology; Investments; Job shop scheduling; Large scale integration; Logic design; Power generation economics; Productivity; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1985.1052343
Filename
1052343
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