DocumentCode :
898800
Title :
Micropower high-performance SC building block for integrated low-level signal processing
Author :
Van Peteghem, Peter M. ; Verbauwhede, Ingrid ; Sansen, Willy M C
Volume :
20
Issue :
4
fYear :
1985
fDate :
8/1/1985 12:00:00 AM
Firstpage :
837
Lastpage :
844
Abstract :
A switched-capacitor instrumentation amplifier which uses correlated-double sampling to reduce the amplifier offset is discussed. Additional offset caused by clock-related charge injection is cancelled by a symmetrical differential circuit topology and a three-phase clocking scheme. An experimental low-power test cell has been integrated, showing 100 μV equivalent offset voltage and input noise equal to 270 μV. For a fixed gain equal to 10- and 9-kHz sampling frequency, the power dissipation is 36 μW (power supply: 5 V); the circuit measures only 0.2 mm/SUP 2/.
Keywords :
CMOS integrated circuits; Instrumentation amplifiers; Signal processing equipment; Switched capacitor networks; instrumentation amplifiers; signal processing equipment; switched capacitor networks; Circuit testing; Circuit topology; Clocks; Frequency; Instruments; Noise cancellation; Sampling methods; Signal processing; Signal sampling; Voltage;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1985.1052397
Filename :
1052397
Link To Document :
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