DocumentCode
898886
Title
Synchronization reliability in CMOS technology
Author
Flannagan, Stephen T.
Volume
20
Issue
4
fYear
1985
fDate
8/1/1985 12:00:00 AM
Firstpage
880
Lastpage
882
Abstract
The synchronization performance of CMOS circuits is examined theoretically and experimentally. Criteria for maximizing CMOS gain are determined and are then compared with NMOS gain curves. The phase characteristics of metastability are identified. Experimental measurements of error rate are made on a CMOS test circuit, and the gain-bandwidth product for the circuit is determined from these data.
Keywords
CMOS integrated circuits; Circuit reliability; Synchronisation; circuit reliability; synchronisation; CMOS technology; Circuit faults; Circuit testing; Differential equations; Error analysis; Geometry; MOS devices; Metastasis; Synchronization; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1985.1052405
Filename
1052405
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