Title :
A reliable 1-Mbit DRAM with a multi-bit-test mode
Author :
Kumanoya, Masaki ; Fujishima, Kazuyasu ; Miyatake, Hideshi ; Nishimura, Yasumasa ; Saito, Kazunori ; Matsukawa, Takayuki ; Yoshihara, Tsutomu ; Nakano, Takao
Abstract :
A single 50V supply 1-Mb DRAM using a half V/SUB cc/ biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide world-line technology.
Keywords :
Field effect integrated circuits; Integrated memory circuits; Random-access storage; field effect integrated circuits; integrated memory circuits; random-access storage; Capacitance; Capacitors; Circuit synthesis; Circuit testing; Random access memory; Read-write memory; Redundancy; Substrates; Switches; Titanium;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1985.1052414
