• DocumentCode
    899014
  • Title

    A 10-/spl mu/W standby power 256K CMOS SRAM

  • Author

    Kobayashi, Yasuo ; Eguchi, Hirotsugu ; Kudoh, Osamu ; Hara, Toshio ; Ooka, Hideyuki ; Sasaki, Isao ; Andoh, Manabu ; Tameda, Masato

  • Volume
    20
  • Issue
    5
  • fYear
    1985
  • Firstpage
    935
  • Lastpage
    940
  • Abstract
    A 32K/spl times/8-bit CMOS static RAM using titanium polycide technology has been developed. The RAM has a standby power of 10 /spl mu/W, an active power of 175 mW, and an access time of 55 ns. The standby power has been achieved by an optimization of polysilicon resistors in a memory cell. A digit line circuit controlled by three internal clocks contributes to reduction of active power. The cell size has been reduced to 89.5 /spl mu/m/SUP 2/ by using both a buried isolation and a polycide GND line. Furthermore a simplified address-transition detection circuit and a single data bus configuration result in a small layout area, thus offering a 40.7 mm/SUP 2/ die size.
  • Keywords
    CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; Circuits; Clocks; Costs; Isolation technology; MOS devices; Power dissipation; Propagation delay; Random access memory; Read-write memory; Titanium;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1985.1052418
  • Filename
    1052418