Title :
An 8-kbit content-addressable and reentrant memory
Author :
Kadota, Hiroshi ; Miyake, Jiro ; Nishimichi, Yoshito ; Kudoh, Hitoshi ; Kagawa, Keiichi
Abstract :
A 256-word/spl times/32-bit associated memory, referred to as the Content Addressable and Reentrant Memory (CARM), with a 100-ns cycle time is described. The high bit density of the device is realized by a small-size associative memory cell (30/spl times/36 /spl mu/m/SUP 2/) with 2-/spl mu/m CMOS technology, while a double-layer metallization technique, new circuits for the control-signal propagation, and a hierarchical structure for the address encoder of the chip allow fast access. This device has reentrant mode operation, where the on-chip garbage collection or data storage is accomplished conditionally. One of the practical applications of this device, a high-speed matching unit for dataflow computers, is also discussed.
Keywords :
CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; Added delay; Application software; Associative memory; CMOS memory circuits; CMOS technology; Clocks; Delay effects; Programmable logic arrays; Random access memory; Registers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1985.1052420
