Title :
A 25-ns 16K CMOS PROM using a four-transistor cell and differential design techniques
Author :
Pathak, Saroj ; Kupec, Jim ; Murphy, Colin ; Sawtelle, Daryl ; Shrivastava, Ritu ; Jenne, Frederick B.
Abstract :
A 25-ns, 250-mW, 2K/spl times/8 PROM using a 1.2-/spl mu/m n-well CMOS technology is described. Speed and programmability are optimized by separating the READ and WRITE transistor functions in a four-transistor differential cell and using differential design techniques. For the first time, a substrate bias generator is used in an EPROM technology to improve speed and raise latch-up immunity to over 200 mA.
Keywords :
CMOS integrated circuits; Integrated memory circuits; PROM; integrated memory circuits; CMOS technology; Design optimization; Dielectric losses; Dielectric substrates; EPROM; Fuses; Nonvolatile memory; PROM; Testing; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1985.1052422
