The design of an IEEE standard math accelerator unit

The design of the WE32106 Math Accelerator Unit, which provides the WE32100 microprocessor with IEEE standard (Draft 10) floating-point capabilities, is described. The chip implements a host of floating-point operations in single, double, and double-extended precision, as well as the complete set of IEEE standard requirements for fault and exception handling. The chip provides a high-speed co-processor interface to the WE32100 microprocessor, as well as a general-purpose memory-mapped peripheral-mode interface to other microprocessors. The chip is implemented in 1.5 /spl mu/m twin-tub CMOS III technology.