DocumentCode
899129
Title
General design principles of totally self-checking code-disjoint inverter-free PLAs
Author
Piestrak, S.J.
Author_Institution
Inst. of Eng. Cybern., Wroclaw Univ. of Technol., Poland
Volume
151
Issue
1
fYear
2004
Firstpage
37
Lastpage
44
Abstract
The author presents a general study of the design of totally self-checking (TSC) code-disjoint (CD) programmable logic arrays (PLAs) under a fault model which covers three classes of PLA faults. It is assumed that both inputs and outputs of a PLA are encoded with an unordered code and that PLAs are inverter-free. It is shown that the necessary condition for TSC and CD properties of a PLA is that the input code is closed. Easily verifyable formal conditions for the existence and verification of a TSC/CD PLA that implements a functional or checking circuit are formulated. The paper tackles the open problem (perhaps the most important for practical applications) of designing TSC/CD PLA-based circuits for highly irregular and incomplete unordered codes which are only required to be composed of some closed unordered subcodes. An important property of all new PLA designs is that they are guaranteed to be crosspoint-irredundant with a test set which is easy to generate. The design approach presented can be readily used for non-PLA circuitry as well.
Keywords
built-in self test; fault simulation; logic CAD; programmable logic arrays; PLA-based circuits; code-disjoint inverter-free PLA; fault model; general design principles; open problem; self-testing; totally self-checking PLA; unordered code;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings -
Publisher
iet
ISSN
1350-2409
Type
jour
DOI
10.1049/ip-cds:20040206
Filename
1267682
Link To Document