DocumentCode :
899184
Title :
Proposal and design of a new SiC-emitter lateral NPM Schottky collector bipolar transistor on SOI for VLSI applications
Author :
Kumar, M. Jagadesh ; Rao, D.V.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India
Volume :
151
Issue :
1
fYear :
2004
Firstpage :
63
Lastpage :
67
Abstract :
A novel bipolar transistor structure, namely, a SiC emitter lateral NPM Schottky collector bipolar transistor (SCBT) with a silicon-on-insulator (SOI) substrate is explored using two-dimensional (2-D) simulation. A comprehensive comparison of the proposed structure with its equivalent Si lateral NPN BJT and an SiC emitter lateral NPN HBT is presented. Based on simulation results, the authors demonstrate for the first time that the proposed SiC emitter lateral NPM transistor shows superior performance in terms of high current gain and cut-off frequency, reduced collector resistance, negligible reverse recovery time and suppressed Kirk effect over its equivalent Si lateral NPN BJT and SiC emitter lateral NPN HBT. A simple fabrication process compatible with BiCMOS technology is also discussed.
Keywords :
BiCMOS integrated circuits; VLSI; heterojunction bipolar transistors; semiconductor device models; silicon compounds; silicon-on-insulator; wide band gap semiconductors; BiCMOS technology; SiC; VLSI applications; bipolar transistor structure; cut-off frequency; fabrication process; high current gain; lateral NPM HBT; lateral NPM Schottky collector; reduced collector resistance; silicon-on-insulator substrate; suppressed Kirk effect; two-dimensional simulation;
fLanguage :
English
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2409
Type :
jour
DOI :
10.1049/ip-cds:20040196
Filename :
1267686
Link To Document :
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