• DocumentCode
    899256
  • Title

    FFT scaling in Domino CMOS gates

  • Author

    Shoji, Masakazu

  • Volume
    20
  • Issue
    5
  • fYear
    1985
  • fDate
    10/1/1985 12:00:00 AM
  • Firstpage
    1067
  • Lastpage
    1071
  • Abstract
    The switching delay of a Domino CMOS gate can be reduced by up to 30% by scaling the NFET chain so that th FET closest to the ground is the largest, with FET size decreasing monotonically from ground to output. The technique is most effective when applied to complex gates, such as those found in a carry look-ahead circuit. The same technique has application to other MOS circuits including NMOS circuits.
  • Keywords
    CMOS integrated circuits; Integrated logic circuits; Logic gates; integrated logic circuits; logic gates; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Delay effects; Equivalent circuits; FETs; MOS devices; Microprocessors; Parasitic capacitance;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1985.1052438
  • Filename
    1052438
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=899256