A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC

Author

Baird, Rex T. ; Fiez, Terri S.

Author_Institution

Crystal Semicond. Corp., Austin, TX, USA

Volume

31

Issue

3

fYear

1996

fDate

3/1/1996 12:00:00 AM

Firstpage

312

Lastpage

320

Abstract

Delta-sigma (ΔΣ) analog-to-digital converters (ADC´s) rely on oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500-kHz ΔΣ ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-μm CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date

Keywords

CMOS integrated circuits; calibration; digital-analogue conversion; sigma-delta modulation; 1.2 micron; 14 bit; 500 kHz; CMOS process; circuit design; circuit topology; delta-sigma analog-to-digital converter; dynamic range; high-order embedded architecture; multibit quantization; oversampling ratio; sampling rate; self-calibrated multibit DAC; stability; Analog-digital conversion; CMOS process; Circuit stability; Circuit synthesis; Circuit topology; Digital modulation; Digital-analog conversion; Dynamic range; Quantization; Robustness;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.494193

Filename

494193