Title :
A 250-MHz skewed-clock pipelined data buffer
Author :
Heshami, Mehrdad ; Wooley, Bruce A.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
fDate :
3/1/1996 12:00:00 AM
Abstract :
A synchronous dual-port memory employing a three-transistor (3T) dynamic cell has been designed for use as a high throughput embedded data buffer in digital switching and signal processing applications. Skewed-clock pipelining is used to achieve operation at frequencies as high as 250 MHz with a low register element count. The 3T cell provides separate read and write access ports while occupying less than half the area of a conventional dual-port SRAM cell. On-chip Hamming error correction coding (ECC) is used to enhance the fault tolerance of the memory, A 25-kb experimental prototype has been integrated in a 0.8-μm CMOS technology; it occupies a die area of 3800 μm×1600 μm and dissipates 420 mW while operating at 250 MHz
Keywords :
CMOS memory circuits; DRAM chips; Hamming codes; buffer storage; error correction; error correction codes; fault tolerant computing; pipeline processing; timing; 0.8 micron; 25 kbit; 250 MHz; 420 mW; CMOS technology; DRAM cell; digital signal processing applications; digital switching applications; dynamic RAM; error correction coding; fault tolerance; high throughput embedded data buffer; onchip Hamming ECC; skewed-clock pipelined data buffer; synchronous dual-port memory; three-transistor dynamic cell; CMOS technology; Computer buffers; Digital signal processing; Error correction codes; Frequency; Pipeline processing; Random access memory; Registers; Signal design; Throughput;
Journal_Title :
Solid-State Circuits, IEEE Journal of
