An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops

Author

Rogenmoser, Robert ; Huang, Qiuting

Author_Institution

Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland

Volume

31

Issue

3

fYear

1996

fDate

3/1/1996 12:00:00 AM

Firstpage

401

Lastpage

409

Abstract

An 8-b adder composed of carry-increment full adders has been designed and implemented in a standard 1.0 μm CMOS technology and successfully tested up to 800 MHz. The performance of this adder is based on a fine-grain pipeline technique using so called “logic-flip-flops”. These edge triggered logic-flip-flops are true single-phase clocked and reduce the cycle time of pipeline stages by combining logic and storage. For low power applications, the power consumption of the 8-b adder can be reduced from 777 mW (5 V Vdd, 800 MHz) down to 144 mW (3 V Vdd, 480 MHz)

Keywords

CMOS logic circuits; adders; flip-flops; pipeline arithmetic; timing; 1 micron; 144 to 777 mW; 3 to 5 V; 480 to 800 MHz; 8 bit; CMOS pipelined adder; carry-increment full adders; clocked logic-flip-flops; edge triggered logic-flip-flops; fine-grain pipeline technique; low power applications; single-phase clocked flip-flops; standard CMOS technology; Adders; CMOS logic circuits; CMOS technology; Clocks; Computer architecture; Energy consumption; Frequency; Logic circuits; Microprocessors; Pipeline processing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.494202

Filename

494202