Title :
A 20-V four-quadrant CMOS analog multiplier
Author :
Babanezhad, Joseph N. ; Temes, Gabor C.
Abstract :
A novel technique is presented for performing the analog multiplication in CMOS technology. The circuit handles a wide range of input voltages. The MSO version of Gilbert´s six-transistor cell (GSTC) is the basis for this multiplier. A simple source-coupled pair is used to study the MOS GSTC. Then, a technique is introduced for linearizing the source-coupled circuit. This scheme is extended to the MOS GSTC. The voltage ranges are further increased by introducing the folded CMOS GSTC.
Keywords :
Active networks; Analogue computer circuits; CMOS integrated circuits; Linear integrated circuits; Multiplying circuits; active networks; analogue computer circuits; linear integrated circuits; multiplying circuits; Bandwidth; Bipolar transistors; CMOS technology; Circuits; Differential amplifiers; Frequency; Nonlinear distortion; Pulsed power supplies; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1985.1052454
