Title :
Discretization error in MOSFET device simulation
Author :
Tanimoto, Hiroyoshi ; Shigyo, Naoyuki
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fDate :
7/1/1992 12:00:00 AM
Abstract :
The discretization error in MOSFET device simulation caused by a coarse grid is discussed. Delaunay and Voronoi discretization grids are used to demonstrate the discretization error. It is possible to clarify the discretization error by using these geometrically complementary grids. An error caused by a coarse grid in the subthreshold region originates from an inaccurate rectangular integral of the carrier density. For the Delaunay grid, the calculated inversion carrier density for a coarse grid is overestimated. In contrast, for the Voronoi grid, the inversion carrier density is underestimated. The equations for estimating the error in the subthreshold region are proposed. In the strong inversion region, the error for the Delaunay grid is smaller than the error in the subthreshold region. On the other hand, for the Voronoi grid, the error is large, even in the strong inversion region. The error for the Voronoi grid in the strong inversion region is caused by a quasi-capacitance originating from discretization
Keywords :
digital simulation; insulated gate field effect transistors; semiconductor device models; Delaunay grid; MOSFET device simulation; Voronoi grid; carrier density; coarse grid; discretization error; discretization grids; geometrically complementary grids; inaccurate rectangular integral; inversion carrier density; quasi-capacitance; strong inversion region; subthreshold region; Capacitance; Charge carrier density; Electromagnetic fields; Electrons; Integral equations; MOSFET circuits; Taylor series; Ultra large scale integration; Upper bound; Voltage;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
