DocumentCode :
899578
Title :
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC
Author :
Arora, Divya ; Raghunathan, Anand ; Ravi, Srivaths ; Sankaradass, Murugan ; Jha, Niraj K. ; Chakradhar, Srimat T.
Author_Institution :
Princeton Univ., Princeton
Volume :
15
Issue :
6
fYear :
2007
fDate :
6/1/2007 12:00:00 AM
Firstpage :
699
Lastpage :
710
Abstract :
The functionality of mobile devices, such as cell phones and personal digital assistants (PDAs), has evolved to include various applications where security is a critical concern (secure web transactions, mobile commerce, download and playback of protected audio/video content, connection to corporate private networks, etc.). Security mechanisms (e.g., secure communication protocols) involve cryptographic algorithms, and are often quite computationally intensive, challenging the constrained processing and battery resources of mobile devices. Extensive design effort and aggressive hardware and software optimizations are required to address this challenge. Previous work has addressed the design of hardware architectures (custom accelerators, domain-specific processors, etc.) to accelerate security processing, and many emerging systems-on-chip (SoCs) feature some form of hardware support for security. In this paper, we address the complementary problem of mapping a complex security software library to an SoC platform with security hardware enhancements. We present a systematic methodology for exploring the software architecture for security processing for a commercial heterogeneous multiprocessor SoC for mobile devices. The SoC contains multiple host processors executing applications and a dedicated programmable security processing engine. We developed an exploration methodology to map the code and data of security software libraries onto the platform, with the objective of maximizing the overall application-visible performance. The salient features of the methodology include: 1) the use of real performance measurements from a prototyping board, which contains the target platform, to drive the exploration; 2) a new data structure access profiling framework that allows us to accurately model the communication overheads involved in off loading a given set of functions to the security processor; and 3) an exact branch-and-bound-based design space exploration algorithm that - determines the best mapping of security library functions and data structures to the host and security processors. We used the proposed framework to map a commercial security library to the target mobile application SoC. The resulting optimized software architecture outperformed several manually designed software architectures, resulting in up to 12.5 times speed-up for individual cryptographic operations (encryption, hashing) and 2.2-6.2 times speed-up for applications such as a digital rights management (DRM) agent and secure sockets layer (SSL) client. We also demonstrate the applicability of our framework to software architecture exploration in other multiprocessor scenarios.
Keywords :
cryptography; embedded systems; portable computers; system-on-chip; branch-and-bound-based design space exploration algorithm; cryptographic operations; data structure access profiling; embedded processor; multiprocessor mobile SoC; programmable security processing engine; security software library mapping; software partitions; systems-on-chip; Application software; Cellular phones; Cryptography; Data security; Data structures; Design optimization; Hardware; Personal digital assistants; Software architecture; Software libraries; Embedded processors; performance; security and protection; software partitioning;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2007.898740
Filename :
4231875
Link To Document :
بازگشت