A 160-kb/s digital subscriber loop transceiver with memory compensation echo canceller

A full-duplex transceiver chip incorporating an adaptive echo canceling modem and a 2.048-Mb/s serial interface is described. The device provides a full-duplex communication link at 160 or 80 kb/s on up to 4 or 5 km, respectively, of 0.5-mm twisted-pair cable. Full integration is achieved through the use of RAM-based sign-algorithm echo-cancellation, biphase line code, a fixed switched-capacitor equalizer, and a digital phase locked loop. The authors emphasize system design considerations and a chip architecture minimizing power dissipation, silicon area, and off-chip components. A double poly 3-μm CMOS technology is used to implement the 5-V 22-pin device which dissipates less than 50 mW and occupies 27.7 mm/SUP 2/.