DocumentCode
900024
Title
Analysis and design of nonequivalent multistage interconnection networks
Author
Agrawal, Dharma P. ; Kim, Seong-Cheol ; Swain, N.K.
Author_Institution
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC
Volume
37
Issue
2
fYear
1988
fDate
2/1/1988 12:00:00 AM
Firstpage
232
Lastpage
237
Abstract
Nonequivalence of multistage interconnection networks is established by obtaining a reduced graph model and then partitioning it into several bipartite subgraphs. This is shown to transform nonequivalence to nonisomorphism, which can be easily determined by examining the intrinsic characteristics of undirected loops. A reverse process allows the design of nonequivalent networks
Keywords
equivalence classes; graph theory; multiprocessor interconnection networks; bipartite subgraphs; nonequivalent multistage interconnection networks; nonisomorphism; reduced graph model; Circuit faults; Circuit testing; Compaction; Counting circuits; Fault tolerance; Feedback; Input variables; Multiprocessor interconnection networks; Pervasive computing; Shift registers;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.2154
Filename
2154
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