DocumentCode
900025
Title
A one-day chip: an innovative IC construction approach using electrically reconfigurable logic VLSI with on-chip programmable interconnections
Author
Ikawa, Yasuo ; Urui, Kiyoshi ; Wada, Masashi ; Takada, Tomoji ; Kawamura, Masahiko ; Miyata, Misao ; Amano, Noboru ; Shibata, Tadashi
Volume
21
Issue
2
fYear
1986
fDate
4/1/1986 12:00:00 AM
Firstpage
223
Lastpage
227
Abstract
A new custom IC design methodology and the associated logic VLSI chip, which offer an ultimately fast turnaround-time logic IC construction method, are proposed. The chip contains various kinds of logic functional blocks, such as inverters, NORs, NANDs, flip-flops, shift registers, counters, adders, multiplexers, and ALUs. Up to 200 SSI/MSI standard logic blocks can be provided. The E/SUP 2/PROM-type MOSFET switch matrix is adjacent to the functional blocks, in order to connect any output to specific inputs of the functional blocks. It also offers a ready-to-test aid, obtained by monitoring the signal waveform developed inside the chip. These features have the advantage over the present custom IC design methods (gate array, standard cell, silicon compiler, programmable logic array) that the designer can easily redesign the logic to obtain a digital system in an IC in a single day.
Keywords
Field effect integrated circuits; Integrated logic circuits; PROM; VLSI; field effect integrated circuits; integrated logic circuits; Design methodology; Digital integrated circuits; Flip-flops; Logic design; Programmable logic arrays; Pulse inverters; Reconfigurable logic; Shift registers; Switches; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1986.1052507
Filename
1052507
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