Title :
Delay-time evaluation in ED MOS logic LSI
Author :
Auvergne, D. ; Cambon, G. ; Deschacht, D. ; Robert, M. ; Sagnes, G. ; Tempier, V.
fDate :
4/1/1986 12:00:00 AM
Abstract :
An explicit formulation of the transient response of ED MOS logic gates is presented, including load conditions and driving waveforms. Defining delays as the time required by the current imbalance of the active inverter to charge or discharge the output load, with respect to physical reference levels, rise and fall mode delay times are obtained in an explicit formulation, with separate contributions due to fan-out and fan-in. Results are applied to ring oscillators and to depletion-load inverter chains with different configuration ratio values and are compared with SPICE simulations. With good agreement obtained, optimal structures with a low value of the configuration ratio can be defined. Analysis of propagation delay times in NOR, NAND, and transmission gates is given, allowing easy implementation of this model into logic simulators.
Keywords :
Field effect integrated circuits; Insulated gate field effect transistors; Integrated logic circuits; Large scale integration; Semiconductor device models; field effect integrated circuits; insulated gate field effect transistors; integrated logic circuits; large scale integration; semiconductor device models; Analytical models; Circuit simulation; Delay effects; Inverters; Large scale integration; Logic circuits; Predictive models; Propagation delay; Ring oscillators; SPICE;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1986.1052525
