Title :
An efficient CMOS buffer for driving large capacitive loads
Author :
Wong, Stephen L. ; Salama, C. Andre T
fDate :
6/1/1986 12:00:00 AM
Abstract :
A CMOS class AB high-drive buffer suitable for driving large capacitive and moderate resistive loads is presented. The buffer, designed using 3-μm technology, occupies only 100 mils/SUP 2/ of area and dissipates 1.5 mW of DC power from a ±2.5-V supply, yet it is capable of driving a 5000-pF capacitor at over 100-kHz clocking frequency. The buffer achieves good slew rate and fast settling by entering into a high-drive state during slewing and returning to a low-power wide-band state during the settling period. Unconditional stability is attained when C/SUB L/≥100 pF and R/SUB L/≥10 kΩ. Total harmonic distortion is below 0.5% for over 70% of the full supply range.
Keywords :
Buffer circuits; buffer circuits; CMOS technology; Capacitance; Capacitors; Circuit stability; Clocks; Dynamic range; Frequency; Operational amplifiers; Total harmonic distortion; Wideband;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1986.1052552