A New Systolic Architecture for Modular Division

Author

Chen, Gang ; Bai, Guoqiang ; Chen, Hongyi

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing

Volume

56

Issue

2

fYear

2007

Firstpage

282

Lastpage

286

Abstract

A new systolic architecture for modular division is proposed in this paper. The architecture is based on a new hardware algorithm for modular division that is extended from the plus-minus algorithm for the greatest common divisor computation. Both the area complexity and the time complexity of the new architecture are linear with respect to the operand bit length. Compared to the architecture using a redundant number representation proposed by Kaihara and Takagi, the new architecture allows a doubled throughput due primarily to the greatly reduced critical path delay, while the area is only about 20 percent larger. Moreover, it is shown that, with a small addition to the control logic, the architecture can also be used to perform Montgomery modular multiplication, thereby efficiently realizing a unified modular multiplier/divider

Keywords

computational complexity; digital arithmetic; parallel algorithms; systolic arrays; Montgomery modular multiplication; area complexity; computer arithmetic; greatest common divisor computation; hardware algorithm; modular division; modular multiplier/divider; plus-minus algorithm; public key cryptosystems; systolic architecture; time complexity; Computational complexity; Computer architecture; Delay; Digital arithmetic; Elliptic curve cryptography; Hardware; Logic; Pipeline processing; Public key cryptography; Throughput; Modular division; computer arithmetic; hardware algorithm; public key cryptosystems.; systolic architecture;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.2007.20

Filename

4042687