A 0.85-ns 1-kbit ECL RAM

Author

Miyanaga, Hiroshi ; Konaka, Shinsuke ; Kobayashi, Yoshiji ; Yamamoto, Yousuke ; Sakai, Tetsushi

Volume

21

Issue

4

fYear

1986

fDate

8/1/1986 12:00:00 AM

Firstpage

501

Lastpage

504

Abstract

A 1-kb ECL RAM with an address access time of 0.85 ns is described. This excellent performance is achieved by combining super self-aligned technology (SST) with 1-μm design rules and high-speed circuit design. SST provides a narrow emitter stripe width of 0.5 μm and a high cutoff frequency of 12.4 GHz at V/SUB CE/=3 V. A two-level metallization process is used. The minimum metallization pitches are 3 μm in the first layer and 6 μm in the second one. The chip size is 2.5×2.5 mm/SUP 2/ and the power dissipation is 950 mW. This RAM is promising for use in super computers and/or high-speed digital systems.

Keywords

Bipolar integrated circuits; Emitter-coupled logic; Integrated circuit technology; Integrated memory circuits; Large scale integration; Random-access storage; bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; Circuit simulation; Circuit synthesis; Cutoff frequency; Decoding; Noise reduction; Parasitic capacitance; Power dissipation; Read-write memory; Resistors; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1986.1052563

Filename

1052563