A GaAs 8×8-bit multiplier/accumulator using JFET DCFL

A description is given of a GaAs JFET LSI circuit containing approximately 1800 gates. The LSI circuit is composed of an 8×8-bit parallel multiplier and a 20-bit accumulator, and uses direct-coupled FET logic (DCFL) circuitry. Fully functional 8×8-bit multipliers have been fabricated and have displayed a multiplication time of 6.0 ns with a power dissipation of 876 mW, operating at a supply voltage of 1.46 V. The 20-bit accumulators have also shown complete operation at a supply voltage of 1.3 V. This LSI circuit is designed to operate in a pipelined fashion using a single clock. The design of the multiplier and the accumulator, the fabrication technology, and the performance of the complete chip are also discussed.