DocumentCode
900997
Title
Performance driven bus buffer insertion
Author
Tsai, Chia-Chun ; Kao, De-Yu ; Cheng, Chung-Kuan
Author_Institution
Dept. of Electron. Eng., Nat. Taiwan Inst. of Technol., Taipei, Taiwan
Volume
15
Issue
4
fYear
1996
fDate
4/1/1996 12:00:00 AM
Firstpage
429
Lastpage
437
Abstract
In this paper, we propose a heuristic algorithm for a given topology of a multisource multisink bus to reduce the signal delay time. The algorithm minimizes the delay by inserting buffers into the candidate locations and sizing the buffers. When compared with the traditional method of source driver sizing, experiments show up to 7.2%, 20.7%, and 29.6% improvement in delay for 2.0, 0.5, and 0.3 μm technologies, respectively
Keywords
VLSI; buffer circuits; circuit layout CAD; delays; integrated circuit layout; logic CAD; network routing; 0.3 to 2 micron; heuristic algorithm; multisource multisink bus; performance driven bus buffer insertion; signal delay time reduction; CMOS analog integrated circuits; CMOS digital integrated circuits; Capacitance; Delay effects; Driver circuits; Heuristic algorithms; Routing; Timing; Topology; Very large scale integration;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.494706
Filename
494706
Link To Document