Title :
25-ns 256K×1/64K×4 CMOS SRAM´s
Author :
Kayano, Shinpei ; Ichinose, Katsuki ; Kohno, Yoshio ; Shinohara, Hirofumi ; Anami, Kenji ; Murakami, Shuji ; Wada, Tomohisa ; Kawai, Yuji ; Akasaka, Yoichi
fDate :
10/1/1986 12:00:00 AM
Abstract :
Through a metal option, a 256K word×1-bit and a 64K word×4-bit CMOS SRAM organization has been obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address-transition-detector circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-μm double-polysilicon and single-metal process technology with a polycide gate offers a memory cell size of 90 μm/SUP Z/ and a chip size of 47.4 mm/SUP 2/.
Keywords :
CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; Circuit synthesis; Decoding; Delay effects; Large scale integration; Parasitic capacitance; Pulse amplifiers; Random access memory; Read-write memory; Research and development; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1986.1052596
