DocumentCode :
901021
Title :
Two-13 ns-64K CMOS SRAM´s with very low active power and improved asynchronous circuit techniques
Author :
Flannagan, Stephen T. ; Reed, Paula ; Voss, Peter H. ; Nogle, Scott G. ; Day, Lawrence J. ; Sheng, David Y. ; Barnes, John J. ; Kung, Roger I.
Volume :
21
Issue :
5
fYear :
1986
fDate :
10/1/1986 12:00:00 AM
Firstpage :
692
Lastpage :
703
Abstract :
64K×1 and 16K×4 CMOS SRAMs which achieve an access time of 13 ns and less than 12-mA active current at 10 MHz are described. A double-metal 1.5-μm p-well process is used. A chip architecture with local amplification improves signal speed and data integrity. Address stability detection techniques are introduced as a method of assuring full asynchronicity over a wide range of conditions. A chip-select speed-up circuit allows high-speed access from a power-down mode. A memory cell design is presented which has improved layout efficiency (area of 189 μm/SUP 2/), yet provides a very high cell ratio of 3:1 for signal stability and margin. Experimental results are presented which demonstrate full performance under address skews and other asynchronous input conditions. High-speed enable access and address access are observed over a wide range of operating conditions.
Keywords :
CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; Asynchronous circuits; Capacitance; Circuit stability; Circuit synthesis; Circuit testing; Memory architecture; Random access memory; Signal design; Timing; Variable speed drives;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1986.1052597
Filename :
1052597
Link To Document :
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