DocumentCode
901024
Title
Addendum to “Synthesis of robust delay-fault testable circuits: Theory”
Author
Devadas, Srinivas ; Keutzer, Kurt
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Volume
15
Issue
4
fYear
1996
fDate
4/1/1996 12:00:00 AM
Firstpage
445
Lastpage
446
Abstract
For original paper see ibid., vol. 11, pp. 87-101 (Jan. 1992). The robust nature of the gate delay fault tests corresponding to Theorems 7 and 8 in the original paper is clarified and described in greater detail. There are two types of robust tests for gate delay faults: a hazard-free robust test for a gate delay fault on a gate g is a robust test where only paths that pass through g are event sensitized; a general robust test for a gate delay fault on a gate g is a robust test where paths that do not pass through g can be event sensitized. The two types of robust tests are illustrated
Keywords
delays; hazards and race conditions; logic testing; multivalued logic circuits; event sensitization; gate delay fault tests; general robust test; hazard-free robust test; multilevel circuit; robust delay-fault testable circuits; Algorithm design and analysis; Circuit faults; Circuit synthesis; Circuit testing; Delay; Design automation; Inverters; Robustness; Sufficient conditions;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.494708
Filename
494708
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