Novel circuit techniques for zero-power 25-ns CMOS erasable programmable logic devices (EPLDs)

A family of CMOS erasable programmable logic devices (EPLDs) is described with emphasis on the state-of-the-art chip architecture and circuit design techniques. The main features of this family of EPLDs include zero standby power, high-speed operation, flip-flop reconfigurability, small chip size, and high reliability. A novel input-transition-detection circuit allows the chip to consume no power during standby and yet wakes the chip up with minimum delay. Basic architectural differences between EPLDs and EPROM are discussed that require extra design considerations to achieve an optimal speed path through the array. A direct-drive technique is used in the transistor-transistor logic buffer and flip-flop circuits to improve speed, layout area, and chip organization.