Title :
Balanced delay trees and combinatorial division in VLSI
Author :
Zuras, Dan ; Mcallister, William H.
fDate :
10/1/1986 12:00:00 AM
Abstract :
Three floating-point arithmetic chips have been implemented in 1.5-μm NMOS technology utilizing several novel circuit designs. The theories behind two of these are presented. A method is presented for constructing balanced delay trees that have a better area-time product than binary trees; one important application of these trees is in the construction of fast multipliers. Also presented is a technique for doing redundant digital division that lends itself to implementation in combinatorial VLSI.
Keywords :
Combinatorial circuits; Delay circuits; Digital arithmetic; Field effect integrated circuits; Integrated logic circuits; VLSI; combinatorial circuits; delay circuits; digital arithmetic; field effect integrated circuits; integrated logic circuits; Adders; Binary trees; Circuit synthesis; Circuit topology; Delay; Floating-point arithmetic; MOS devices; Standards development; Very large scale integration; Wires;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1986.1052612
