DocumentCode
901228
Title
Silicon hybrid wafer-scale package technology
Author
Johnson, Wayne R. ; Davidson, Jim L. ; Jaeger, Richard C. ; Kerns, David V., Jr.
Volume
21
Issue
5
fYear
1986
fDate
10/1/1986 12:00:00 AM
Firstpage
845
Lastpage
851
Abstract
A wafer-scale packaging technology is discussed. Pretested IC chips are mounted in holes etched through silicon wafers. Chips are interconnected via the wafer using standard multilevel metallization processes. The packaging technology has the potential to provide the flexibility of hybrid techniques with the reliability and density of monolithic fabrication.
Keywords
Hybrid integrated circuits; Integrated circuit technology; Metallisation; Monolithic integrated circuits; Packaging; hybrid integrated circuits; integrated circuit technology; metallisation; monolithic integrated circuits; packaging; Assembly; Electronics packaging; Etching; Integrated circuit interconnections; Integrated circuit technology; Metallization; Microelectronics; Semiconductor device packaging; Silicon; Wafer scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1986.1052616
Filename
1052616
Link To Document