Title :
The design of TSC error C/D circuits for SEC/DED codes
Author :
Gaitanis, Nicolaos
Author_Institution :
Dept of Comput., NRC Democritos, Athens, Greece
fDate :
3/1/1988 12:00:00 AM
Abstract :
A design technique for totally self-checking (TSC) error correcting/detection (C/D) circuits of single error correcting, double error detection (SEC/DED) codes is described. The structure of these circuits achieves concurrent fault detection and location under normal input conditions. A separate internal fault indication is provided. This improves the reliability, maintainability, and availability of the entire fault-tolerant system because faults are repaired before the appearance of input errors. The error C/D circuits are composed of TSC error detectors, error locators, and error correctors. These circuits are two-rail TSC checkers and are designed using an algebraic approach
Keywords :
automatic testing; error correction codes; error detection codes; fault tolerant computing; logic testing; availability; codes; concurrent fault detection; double error detection; error correction circuits; error detection circuits; error locators; fault-tolerant system; maintainability; reliability; single error correcting; totally self-checking; Circuit faults; Computer errors; Costs; Detectors; Electrical fault detection; Error correction; Error correction codes; Fault detection; Fault diagnosis; Maintenance;
Journal_Title :
Computers, IEEE Transactions on
