Title :
A 12-bit successive-approximation-type ADC with digital error correction
fDate :
12/1/1986 12:00:00 AM
Abstract :
A correction algorithm has been implemented that gives an almost twofold improvement in conversion speed without loss of accuracy or changes to the analog circuitry of a slower design. The design of a smart successive-approximation register chip, which has been fabricated in a double poly CMOS process and takes up 18 mil/SUP 2/ in die area, is described. The area is 13% larger than that of an A/D converter utilizing the same analog chip but a conventional digital chip without error correction. A speed improvement from 12 to 7 μs was obtained with digital error correction.
Keywords :
Analogue-digital conversion; CMOS integrated circuits; Error correction; analogue-digital conversion; error correction; Analog-digital conversion; Approximation algorithms; CMOS process; Circuits; Digital-analog conversion; EPROM; Error correction; Registers; Signal resolution; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1986.1052644
