Ionizing Radiation Response of GaAs JFETs and DCFL Circuits

Transient responses and logic upset threshold dose rates of planar, all-ion implanted GaAs E-JFETs and DCFL (= direct-coupled field-effect transistor logic) integrated circuits to ionizing radiation pulses of 20 ns duration from a LINAC are reported. It is experimentally verified that the logic upset dose rate of enhancement mode GaAs JFET integrated circuits is inversely proportional to the square of their channel length. For L = 1 ¿m a theoretical value of ¿UPSET = 1.175 × 1011 rad (GaAs)/s is predicted and medium scale integrated circuits have confirmed this value with experimental results in the range of 5 × 1010 to 1 × 1011 rad (GaAs)/s. A theoretical relation for logic upset dose rate and a correlation of experimental results with theory is presented. Long term conductance transients are not inherent to E-JFET inverters with resistive and depletion mode JFET load, but are present in source-follower circuits. A model for this circuit behavior will be presented.