Title :
A high-speed high-density silicon 8×8-bit parallel multiplier
Author :
Lee, Joseph Y. ; Garvin, Hugh L. ; Slayman, Charles W.
fDate :
2/1/1987 12:00:00 AM
Abstract :
An 8×8-bit parallel multiplier with submicrometer gate lengths has been fabricated using silicon NMOS technology. The multiplication time is 9.5 ns. This corresponds to an average loaded gate delay in the multiplier circuit of 244 ps/gate, which the authors believe is the shortest gate delay for MOS multiplier circuits demonstrated to date. The power dissipation is 600 mW at a supply voltage of 5 V. The multiplier circuit has a total of 1427 transistors in an active area of 0.61×0.58 mm/SUP 2/, corresponding to a gate density of 1125 gates/mm/SUP 2/.
Keywords :
Digital arithmetic; Elemental semiconductors; Field effect integrated circuits; Integrated logic circuits; Large scale integration; Multiplying circuits; Silicon; digital arithmetic; elemental semiconductors; field effect integrated circuits; integrated logic circuits; large scale integration; multiplying circuits; silicon; Adders; Circuit synthesis; Delay; Driver circuits; Joining processes; Logic circuits; Silicon; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052668
