Signal integrity and timing issues of VME64x double edge cycles

The Double-Edge Source Synchronous Block Transfer (2eSST) is the latest performance update to the VME64 protocol, approved as an ANSI standard in 2003. This extension has taken the VMEs data transfer rate from the original 40 MByte/s to 320 MByte/s. The architectural change at the base of such an impressive step forward is twofold. Different from all the previous cycles, data transfers are driven synchronously by the producer, without handshaking, and data is latched on both the rising and falling edges of the strobe signal. The double edge clocking effectively doubles the bandwidth and it is normally present on PC motherboards equipped with double data rate RAM chips and high-performance graphic adapters. In these applications, a careful approach to signal integrity has shown to be critical in order to avoid timing violations. In parallel, multidrop bus architecture with long lines and up to 21 slots, these concerns become imperative for successful operations. In this paper we present the tests performed on 2eSST. The Motorola MVME6100 and a custom designed board have been used to characterize the timing with different bus loading conditions and to evaluate the impact of different layout choices. Driving capability and crosstalk immunity of enhanced transceivers specifically developed for 2eSST and traditional components are compared.