DocumentCode
902094
Title
A high-performance custom standard-cell CMOS equalizer for telecommunications applications
Author
Rahim, Chowdhury F. ; Laber, Carlos A. ; Pickett, Bradley L. ; Baechtold, Fred J.
Volume
22
Issue
2
fYear
1987
fDate
4/1/1987 12:00:00 AM
Firstpage
174
Lastpage
180
Abstract
A high-performance CMOS programmable amplitude equalizer has been implemented with a dynamic range greater than 100 dB and supply rejection greater than 60 dB at 1 kHz from both supplies. This was accomplished using a balanced architecture. A nonreturn-to-zero sample-and-hold circuit is proposed that is also parasitic-insensitive. The circuits are implemented using a standard-cell methodology.
Keywords
CMOS integrated circuits; Equalisers; equalisers; Band pass filters; Circuit noise; Codecs; Degradation; Digital filters; Dynamic range; Equalizers; Frequency; Poles and zeros; Telephony;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052699
Filename
1052699
Link To Document