Title :
PLA folding by simulated annealing
Author :
Wong, D.F. ; Leong, H.W. ; Laung, C.L.
fDate :
4/1/1987 12:00:00 AM
Abstract :
A simulated-annealing programmable-logic array (PLA) folding algorithm is presented for simple as well as multiple-column folding. Experimental results indicate that the algorithm performs very well. In many test problems, the results are superior to those produced by the well-known heuristic algorithm of G. De Micheli and A. Sangiovanni-Vincentelli (1983). It is also shown that the algorithm can be extended to handle constrained folding.
Keywords :
Cellular arrays; Integrated logic circuits; Logic design; cellular arrays; integrated logic circuits; logic design; Circuit simulation; Computational modeling; Continuous wavelet transforms; Heuristic algorithms; Input variables; Logic arrays; Process design; Programmable logic arrays; Simulated annealing; Testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052704
