Title :
Path Selection for Transition Path Delay Faults
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fDate :
3/1/2010 12:00:00 AM
Abstract :
We propose a path selection criterion to improve the coverage of small delay defects. Under this criterion, every line in the circuit is covered by one of the longest testable paths or subpaths that goes through it. Earlier criteria that considered only complete paths (from inputs to outputs) did not use longest testable subpaths, which may be longer than the longest complete testable paths. Earlier criteria that considered subpaths considered only subpaths of longest paths. We apply the proposed criterion to a delay fault model called the transition path delay fault model. This model was introduced to capture both small and large delay defects. We present experimental results to demonstrate that consideration of subpaths improves the circuit coverage relative to the case where only complete paths are allowed.
Keywords :
circuit reliability; circuit testing; fault simulation; large delay defects; path selection; small delay defects; transition path delay fault model; transition path delay faults; Path delay faults; path selection; test generation; transition faults;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2008.2011913