DocumentCode
902827
Title
Fast convergent pipelined adaptive DFE architecture using post-cursor processing filter technique
Author
Yang, Meng-Da ; Wu, An-Yeu ; Lai, Jyh-Ting
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
51
Issue
2
fYear
2004
fDate
2/1/2004 12:00:00 AM
Firstpage
57
Lastpage
60
Abstract
Among existing works of high-speed pipelined adaptive decision feedback equalizers (ADFE), the pipelined ADFE using relaxed look-ahead technique results in a substantial hardware saving than the parallel processing or other look-ahead approaches. For example, Shanbhag and Partiz derived three pipeline ADFE structures (PIPEADFE1, 2, 3), where PIPEADFE2 yields very good performance in terms of convergence rate and hardware cost. Nevertheless, the PIPEADFE2 employs Approximation Methods in deriving the Preprocessing Unit (PP). In this paper, a new pipelining ADFE architecture is developed. We derive a new updating ADFE scheme based on the Principle of Orthogonality. By employing the postcursor processing filter (PCF) to cancel the most significant postcursor Intersymbol interference (ISI) terms, the proposed PCFADFE architecture can significantly improve the convergence rate of the ADFE. Compared with PIPEADFE2, it has better convergence rate while at similar hardware cost. Hence, it provides an alternative approach for the design of high-speed pipelining ADFE with arbitrary speedup factor.
Keywords
adaptive equalisers; decision feedback equalisers; pipeline arithmetic; adaptive decision feedback equalizers; arbitrary speedup factor; convergence rate; convergent pipelined adaptive DFE architecture; hardware cost; parallel processing; post-cursor processing filter; postcursor Intersymbol interference; postcursor processing filter; preprocessing unit; principle of orthogonality; relaxed look-ahead technique; Adaptive filters; Approximation methods; Convergence; Costs; Decision feedback equalizers; Hardware; Interference cancellation; Intersymbol interference; Parallel processing; Pipeline processing;
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2003.822421
Filename
1268236
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