Title :
2.7 ns 8×8-bit parallel array multiplier user sidewall base contact structure
Author :
Washio, Katsuyoshi ; Nakazato, Kazuo ; Nakamura, Tohru
fDate :
8/1/1987 12:00:00 AM
Abstract :
A high-speed 8×8-b parallel array multiplier is developed using sidewall base contact structure (SICOS) technology. The two´s-complement multiplication algorithm with carry save adder arrays and carry lookahead adders is utilized. A SICOS transistor results in 14-GHz cutoff frequency and 84-ps/gate ECL switching speed. Multiplication is 2.7 ns with a power dissipation of 900 mW.
Keywords :
Bipolar integrated circuits; Carry logic; Cellular arrays; Digital arithmetic; Integrated logic circuits; Multiplying circuits; Parallel processing; bipolar integrated circuits; carry logic; cellular arrays; digital arithmetic; integrated logic circuits; multiplying circuits; parallel processing; Adders; Cutoff frequency; Parasitic capacitance; Power dissipation; Propagation delay; Pulse measurements; Semiconductor device measurement; Signal processing algorithms; Silicon; Transistors;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052779
