Title :
A content addressable memory with a fault-tolerance mechanism
Author :
Blair, Gerard Miles
fDate :
8/1/1987 12:00:00 AM
Abstract :
The use of a latch-based fault-tolerance mechanism is described in the design of a word-parallel content-addressable memory, using test circuitry and addressing mechanisms which are already in place at a cost of only a 4% increase in the word area.
Keywords :
Content-addressable storage; Fault tolerant computing; Field effect integrated circuits; Integrated memory circuits; VLSI; content-addressable storage; fault tolerant computing; field effect integrated circuits; integrated memory circuits; Associative memory; CADCAM; Circuit faults; Circuit testing; Computer aided manufacturing; Fault tolerance; Logic; Power dissipation; Read-write memory; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052780
