DocumentCode
903298
Title
A 40-ns/100-pF low power full-CMOS 256 K (32 K×8) SRAM
Author
Gubbels, Will C H ; Hartgring, Cornelis D. ; Salters, Roelof H W ; Lammerts, Jos A M ; Tooher, Michael J. ; Hens, Patrick F P C ; Bustiaens, J.J.J. ; Van Dijk, Jan M F ; Sprokel, Marc A.
Volume
22
Issue
5
fYear
1987
fDate
10/1/1987 12:00:00 AM
Firstpage
741
Lastpage
747
Abstract
A fast and low-power full-CMOS 256 K (32 K×8-b) static RAM is described. Typical access time is 40 ns with a 100-pF load. Power dissipation is 100 mW at 10 MHz and <1 μW in standby mode. The low standby power has been achieved by introducing a novel six-transistor, polysilicon-interconnected, double-cross-coupled cell. A novel output buffer design, a data-transition detection (DTD) circuit, and several other circuit techniques are introduced to obtain the speed and low active power dissipation. This chip is made in a 1.3-μm, twin-tub, single-poly, double-metal technology with a p epi layer on p/SUP +/ substrate.
Keywords
CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; CMOS process; CMOS technology; Circuits; Impedance; Laboratories; Power dissipation; Random access memory; Read-write memory; Subthreshold current; Transistors;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052808
Filename
1052808
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