A sub-10-ns 16×16 multiplier using 0.6-μm CMOS technology

Author

Oowaki, Yukihito ; Numata, Kenji ; Tsuchiya, Kenji ; Tsuda, Kazushi ; Takato, Hiroshi ; Takenouchi, Naoko ; Nitayama, Akihiro ; Kobayashi, Takayuki ; Chiba, Masahiko ; Watanabe, Shigeyoshi ; Ohuchi, Kazunori ; Hojo, Akimichi

Volume

22

Issue

5

fYear

1987

fDate

10/1/1987 12:00:00 AM

Firstpage

762

Lastpage

767

Abstract

A 16×16-b parallel multiplier fabricated in a 0.6-μm CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth´s algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-μm CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.

Keywords

CMOS integrated circuits; Cellular arrays; Digital arithmetic; Integrated logic circuits; Multiplying circuits; Parallel processing; cellular arrays; digital arithmetic; integrated logic circuits; multiplying circuits; parallel processing; Arithmetic; CMOS technology; Digital signal processing; Energy consumption; Gallium arsenide; Logic devices; Manufacturing; Registers; Signal generators; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1987.1052811

Filename

1052811