Title :
Application of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technology
Author :
Bafleur, M. ; Buxo, J. ; Vidal, Puig M. ; Givelin, P. ; Macary, V. ; Sarrabayrouse, G.
Author_Institution :
Lab. d´´Autum. et d´´Anal. des Syst., CNRS, Toulouse, France
fDate :
7/1/1993 12:00:00 AM
Abstract :
An original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology is presented. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up
Keywords :
MOS integrated circuits; power integrated circuits; switching circuits; MOS transistors; cost-effective technology; design methodology; floating well concept; high-side switch technology; latch-up-free; smart power; Automotive applications; CMOS logic circuits; CMOS technology; Diodes; Leakage current; MOSFETs; Switches; Switching circuits; Tellurium; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
