• DocumentCode
    903467
  • Title

    A 7-ns/350-mW 64-kbit ECL-compatible RAM

  • Author

    Miyaoka, Shuuichi ; Odaka, Masanori ; Ogiue, Katsumi ; Ikeda, Takahide ; Suzuki, Makoto ; Higuchi, Hisayuki ; Hirao, Mitsuru

  • Volume
    22
  • Issue
    5
  • fYear
    1987
  • fDate
    10/1/1987 12:00:00 AM
  • Firstpage
    847
  • Lastpage
    849
  • Abstract
    A 7-ns 350-mW, 64-kbit ECL RAM was developed using 1.3-μm high-performance bipolar-CMOS (Hi-BiCMOS) technology, in which a bipolar transistor of 7-GHz cutoff frequency is fabricated together with 1.3-μm CMOS. A variable-impedance data-line load, a common data-line equalizing circuit, and a sense-amplifier selection technique together achieve a 7-ns access time. Gates combining bipolar and CMOS devices achieve a power dissipation of one-third that of conventional bipolar 64-kb ECL RAMs.
  • Keywords
    Emitter-coupled logic; Integrated memory circuits; Monolithic integrated circuits; Random-access storage; emitter-coupled logic; integrated memory circuits; monolithic integrated circuits; random-access storage; BiCMOS integrated circuits; Bipolar transistors; CMOS technology; Capacitance; Cutoff frequency; Impedance; Large scale integration; MOSFETs; Power dissipation; Read-write memory;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1987.1052822
  • Filename
    1052822
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=903467