Title :
A 7-ns/350-mW 64-kbit ECL-compatible RAM
Author :
Miyaoka, Shuuichi ; Odaka, Masanori ; Ogiue, Katsumi ; Ikeda, Takahide ; Suzuki, Makoto ; Higuchi, Hisayuki ; Hirao, Mitsuru
fDate :
10/1/1987 12:00:00 AM
Abstract :
A 7-ns 350-mW, 64-kbit ECL RAM was developed using 1.3-μm high-performance bipolar-CMOS (Hi-BiCMOS) technology, in which a bipolar transistor of 7-GHz cutoff frequency is fabricated together with 1.3-μm CMOS. A variable-impedance data-line load, a common data-line equalizing circuit, and a sense-amplifier selection technique together achieve a 7-ns access time. Gates combining bipolar and CMOS devices achieve a power dissipation of one-third that of conventional bipolar 64-kb ECL RAMs.
Keywords :
Emitter-coupled logic; Integrated memory circuits; Monolithic integrated circuits; Random-access storage; emitter-coupled logic; integrated memory circuits; monolithic integrated circuits; random-access storage; BiCMOS integrated circuits; Bipolar transistors; CMOS technology; Capacitance; Cutoff frequency; Impedance; Large scale integration; MOSFETs; Power dissipation; Read-write memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052822
