DocumentCode
903719
Title
A pipelined 5-Msample/s 9-bit analog-to-digital converter
Author
Lewis, Stephen H. ; Gray, Paul R.
Volume
22
Issue
6
fYear
1987
fDate
12/1/1987 12:00:00 AM
Firstpage
954
Lastpage
961
Abstract
A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-μm CMOS technology. It requires 8500 mil/SUP 2/, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.
Keywords
Analogue-digital conversion; CMOS integrated circuits; Pipeline processing; analogue-digital conversion; pipeline processing; Analog-digital conversion; CMOS technology; Capacitance; Circuits; Clocks; Costs; Error correction; Image converters; Prototypes; Throughput;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052843
Filename
1052843
Link To Document